1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a driving apparatus for a liquid crystal display that is capable of adjusting a field area displayed on the liquid crystal display panel at the exterior thereof.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) of active matrix driving system uses thin film transistors (TFT's) as switching devices to display moving pictures. Since such a LCD can be made into a device smaller in size than the existent Brown tubes, it has been widely used for a monitor for personal computers or notebook computers as well as office automation equipments such as copy machines, etc. and portable equipments such as cellular phones and pagers, etc.
The active matrix LCD displays a picture corresponding to video signals, such as television signals, on a picture element matrix or pixel matrix having liquid crystal cells arranged at crossings between gate lines and data lines. The thin film transistor is provided at each crossing between the gate lines and the data lines to thereby switch a data signal to be transmitted into the liquid crystal cell in response to a scanning signal (or gate pulse) from the gate line.
Such an LCD is classified into one using NTSC signal system and one using PAL signal system in accordance with television signal system.
Generally, if an NTSC signal (i.e., 525 vertical lines) is inputted, then the horizontal resolution of the LCD is expressed in accordance with the number of sampled data, and the vertical resolution thereof is expressed by a 234 line de-interlace scheme. On the other hand, if a PAL signal (i.e., 625 vertical lines) is inputted, then the horizontal resolution of the LCD is expressed in accordance with the number of sampled data, and the vertical resolution thereof is expressed by a processing system similar to the NTSC signal scheme in which one line is removed from every six vertical lines to be resulted in 521 lines.
Referring to FIG. 1 and FIG. 2, a related art LCD driving apparatus includes a liquid crystal display panel 30 having liquid crystal cells arranged in a matrix type, a gate driver 34 for driving gate lines GL of the liquid crystal display panel 30, a data driver 32 for driving data lines DL of the liquid crystal display panel 30, and an image signal processor 10 for receiving an NTSC television signal to apply a television complex signal divided into RGB data signals R, G and B to the data driver and output a complex synchronizing signal Csync. The LCD driving apparatus further includes a phase locked loop (PLL) control circuit 22 for outputting a phase locked loop and a timing controller 20 for receiving the complex synchronizing signal Csync from the image signal processor 10 to make a divisional output of a horizontal synchronizing signal Hsync and a vertical synchronizing signal Vsync and for applying control signals to the data driver 32 and the gate driver 34 in response to the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync and the PLL control circuit 22 to thereby control a driving timing thereof.
The liquid crystal display panel 30 includes liquid crystal cells arranged in a matrix type and thin film transistors TFT provided at crossings between the gate lines GL and the data lines DL to be connected to the liquid crystal cells.
The thin film transistor TFT is turned on when a scanning signal, that is, a gate high voltage VGH from the gate line GL, is applied, to thereby apply a pixel signal from the data line DL to the liquid crystal cell. On the other hand, the thin film transistor TFT is turned off when a gate low voltage VGL is applied from the gate line GL, to thereby maintain a pixel signal charged in the liquid crystal cell.
The liquid crystal cell can be equivalently expressed as a liquid crystal capacitor LC, and includes a pixel electrode connected to the thin film transistor TFT and a common electrode that are opposed to each other having a liquid crystal therebetween. Further, the liquid crystal cell includes a storage capacitor Cst for making stable maintenance of the charged pixel signal until the next pixel is charged. This storage capacitor Cst is provided between a previous gate line and the pixel electrode. In such a liquid crystal cell, an alignment state of the liquid crystal having a dielectric anisotropy varies in response to the pixel signal charged via the thin film transistor TFT to control a light transmittance, thereby implementing a gray scale level.
The gate driver 34 sequentially applies the gate high voltage VGH to the gate lines GL in response to gate control signals GSP, GSC and GOE from the timing controller 20. Thus, the gate driver 34 drives the thin film transistors TFT connected to the gate lines GL for each gate line.
More specifically, the gate driver 34 shifts a gate start pulse GSP in response to a gate shift pulse GSC to generate a shift pulse. Further, the gate driver 34 applies the gate high voltage VGH to the corresponding gate line GL every horizontal period H1, H2, . . . in response to the shift pulse. In this case, the gate driver 34 applies the gate high voltage VGH only in an enable period in response to a gate output enable signal GOE. On the other hand, the gate driver 34 applies the gate low voltage VGL in the remaining period when the gate high voltage VGH is not applied to the gate lines GL.
The data driver 32 applies pixel data signals for each one line to the data lines DL every horizontal period 1H, 2H, . . . in response to data control signals SSP, SSC and SOE from the timing controller 20. Particularly, the data driver 32 applies RGB data from the image signal processor 10 to the liquid crystal display panel 30.
More specifically, the data driver 32 shifts a source start pulse SSP in response to a source shift clock SSC to generate a sampling signal. Then, the data driver 32 sequentially inputs analog RGB data for each certain unit in response to the sampling signal to latch them. Further, the data driver 32 applies the latched analog data for one line to the data lines DL.
The image signal processor 10 converts image signals applied from the exterior into voltages R, G and B suitable for driving of the liquid crystal display panel 30 in accordance with a property of the liquid crystal display panel 30 to apply them to the data driver 32, and applies a complex synchronizing signal Csync to the timing controller 20. Herein, the complex synchronizing signal Csync is separately generated from the image signal NTSC.
The PLL control circuit 22 generates a phase locked loop PLL having a desired oscillation frequency to apply it to the timing controller 20.
The timing controller 20 includes a frequency divider (not shown) for outputting a frequency-dividing signal DIV having the same period as the complex synchronizing signal Csync and various clocks, and synchronizes the complex synchronizing signal Csync with the frequency-dividing signal DIV with the aid of the phase locked loop PLL. Herein, the frequency-dividing signal DIV is synchronized with a center portion of the width of the complex synchronizing signal Csync. The timing controller 20 generates a horizontal synchronizing signal Hsync inverted from the complex synchronizing signal Csync using various clocks from the frequency divider. Further, as shown in FIG. 3, the timing controller 20 includes a source start pulse generator 24 for generating a source start pulse SSP that determines a horizontal display start time ST of the image signal NTSC displayed on the liquid crystal display panel 30.
The source start pulse generator 24 receives the complex synchronizing signal Csync from the image signal processor 10, and receives the frequency-dividing signal DIV and the horizontal synchronizing signal Hsync generated from the internal part of the timing controller 20. Thus, the source start pulse generator 24 generates the source start pulse SSP using the complex synchronizing signal Csync and the frequency-dividing signal DIV, or generates the source start pulse SSP using the complex synchronizing signal Csync and the horizontal synchronizing signal Hsync. The source start pulse SSP from the source start pulse generator 24 is applied to the data driver 32.
Such a related art LCD driving apparatus displays an image from a start time ST of the source start pulse SSP, of an image region of the image signal NTSC, on one horizontal line of the liquid crystal display panel 30 with the aid of the source start pulse SSP. For instance, as shown in FIG. 4, if an image signal expressing 1 to 13 is displayed on one horizontal line of the liquid crystal display panel 30 with the aid of the source start pulse SSP, then an image signal B indicated by the slanted lines, that is, only 3 to 12 are displayed.